SpaceX was founded under the belief that a future where humanity is out exploring the stars is fundamentally more exciting than one where we are not. Today SpaceX is actively developing the technologies to make this possible, with the ultimate goal of enabling human life on Mars.

SR. SOC/ASIC PHYSICAL DESIGN METHODOLOGY/CAD ENGINEER (SILICON ENGINEERING)

At SpaceX we’re leveraging our experience in building rockets and spacecraft to deploy Starlink, the world’s most advanced broadband internet system. Starlink is the world’s largest satellite constellation and is providing fast, reliable internet to millions of users worldwide. We design, build, test, and operate all parts of the system – thousands of satellites, consumer receivers that allow users to connect within minutes of unboxing, and the software that brings it all together. We’ve only begun to scratch the surface of Starlink’s potential global impact and are looking for best-in-class engineers to help maximize Starlink’s utility for communities and businesses around the globe.

We are seeking a motivated, proactive, and intellectually curious engineer who will work alongside world-class cross-disciplinary teams (systems, firmware, architecture, design, validation, product engineering, ASIC implementation). In this role, you will be developing cutting-edge next-generation silicon for deployment in space and ground infrastructures around the globe. These chips are enabling connectivity in places it has previously not been available, affordable or reliable. Your efforts will help deliver cutting-edge solutions that will expand the performance and capabilities of the Starlink network.

RESPONSIBILITIES:

Create and support innovative RTL2GDSII methodology and CAD flows, capable of handling multimillion gate designs for best-in-class PPA and run times
Create integrated hierarchical physical design flow to enable SoC collateral management for PV/STA/EM/IR signoff
Create dashboard/central reports for project tracking and visualizing results/stats
Interface directly with RTL, physical design, package design, DFT and other teams to improve methodologies and efficiencies and drive efforts to resolution
Work with EDA tool vendors to evaluate new tools, solve bugs, improve usability, methodology and design flow
Integrate foundry EDA kits into SpaceX environment, drive vendor IP integration into SpaceX infrastructure
Drive setting up RTL2GDSII flows for brand new technology nodes, run regressions, quality assurance checks, and release high quality flows to execution designers before starting the project
Perform partition synthesis and physical implementation steps (e.g. synthesis, floorplanning, power/ground grid generation, place and route, timing, noise, physical verification, electromigration, voltage drop, logic equivalency and other signoff checks)

BASIC QUALIFICATIONS:

Bachelor’s degree in electrical engineering, computer engineering or computer science
5+ years of experience in the field of Physical Design and/or CAD for RTL2GDSII flows

PREFERRED SKILLS AND EXPERIENCE:

Experience in high-performance, low-power physical design, and implementation techniques with industry standard synthesis, place and route, or signoff tools
Knowledge of cutting-edge technology node across foundries
Excellent programming skills in languages like Python, Perl, TCL, Shell, etc. Good understanding of algorithms with emphasis on optimizing algorithms
Knowledge of creating dashboards and html status reporting systems for various EDA tool outputs (synthesis, place and route, signoff, DFT, etc.)
Experience with machine learning
Excellent verbal and written communications
Ability to work in a dynamic environment with changing needs and requirements
Team-player, can-do attitude and ability to work well in a group environment while still contributing on an individual basis
Enjoys being challenged and learning new skills

ADDITIONAL REQUIREMENTS:

Must be willing to work extended hours and weekends as needed

COMPENSATION AND BENEFITS:

Pay range:
Physical Design Engineer/Senior: $170,000.00 - $230,000.00/per year

Your actual level and base salary will be determined on a case-by-case basis and may vary based on the following considerations: job-related knowledge and skills, education, and experience.

Base salary is just one part of your total rewards package at SpaceX. You may also be eligible for long-term incentives, in the form of company stock, stock options, or long-term cash awards, as well as potential discretionary bonuses and the ability to purchase additional stock at a discount through an Employee Stock Purchase Plan. You will also receive access to comprehensive medical, vision, and dental coverage, access to a 401(k) retirement plan, short & long-term disability insurance, life insurance, paid parental leave, and various other discounts and perks. You may also accrue 3 weeks of paid vacation & will be eligible for 10 or more paid holidays per year. Exempt employees are eligible for 5 days of sick leave per year.

ITAR REQUIREMENTS:

To conform to U.S. Government export regulations, applicant must be a (i) U.S. citizen or national, (ii) U.S. lawful, permanent resident (aka green card holder), (iii) Refugee under 8 U.S.C. § 1157, or (iv) Asylee under 8 U.S.C. § 1158, or be eligible to obtain the required authorizations from the U.S. Department of State. Learn more about the ITAR here.

SpaceX is an Equal Opportunity Employer; employment with SpaceX is governed on the basis of merit, competence and qualifications and will not be influenced in any manner by race, color, religion, gender, national origin/ethnicity, veteran status, disability status, age, sexual orientation, gender identity, marital status, mental or physical disability or any other legally protected status.

Applicants wishing to view a copy of SpaceX’s Affirmative Action Plan for veterans and individuals with disabilities, or applicants requiring reasonable accommodation to the application/interview process should reach out to EEOCompliance@spacex.com.

Sr. SOC/ASIC Physical Design Methodology/CAD Engineer (Silicon Engineering)